Impact of Low-Variability SOTB Process on Ultra-Low-Voltage Operation of 1 Million Logic Gates †

Journal of Low Power Electronics and Applications

Yasuhiro Ogasahara³  Tadashi Nakagawa³  Toshihiro Sekigawa³  Toshiyuki Tsutsumi²  Hanpei Koike³  David Bol¹ 

[1] Electroinformatics Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba 3058568, Japan;;Computer Science Course, Fundamental Science and Technology, Graduate School of Science and Technology, Meiji University, 1-1-1 Higashi-Mita Tama, Kawasaki 2148571, Japan; E-Mail:;Electroinformatics Group, Nanoelectronics Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), 1-1-1 Umezono, Tsukuba 3058568, Japan; E-Mails:

关键词: SOTB;    FD-SOI;    ultra-low voltage;    measurement on silicon;   

DOI  :  10.3390/jlpea5020116

来源: mdpi

【 摘 要 】

In this study, we demonstrate near-0.1 V minimum operating voltage of a low-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates on silicon. Low process variability is required to obtain higher energy efficiency during ultra-low-voltage operation with steeper subthreshold slope transistors. In this study, we verify the decrease in operating voltage of logic circuits via a variability-suppressed SOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and bulk processes, the operating voltage at which the first failure is observed was lowered from 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V, over 40% yield can be expected as per our measurement results on SOTB test chips.

【 授权许可】

CC BY   
© 2015 by the authors; licensee MDPI, Basel, Switzerland.