A VHDL Module Generator for Fast Prototyping of Multimedia ASICS

Malaysian Journal of Computer Science

Kah Hoe Koay¹  Mohamed Khalil Hani¹ 

关键词: VHDL;    module generator;    design entry;    EDA;    CAD;    rapid-prototyping;    parameterized;    JPEG decoder;   

DOI  :  

学科分类：社会科学、人文和艺术（综合）

来源: University of Malaya * Faculty of Computer Science and Information Technology

【 摘 要 】

This paper presents an electronic design automation (EDA) software for generating synthesizable VHDL modules for hardware applications of multimedia data processing. The tool provides a rapid-prototyping design environment by enabling dynamic storage and retrieval of reusable modules, parameterized design entry, hierarchical design exploration, list-based component interface insertion, and block diagram view of designs. This produces a design environment, which enables fast design development cycle by improving design productivity to meet the fast evolving standards of multimedia formats. A test case design of a JPEG decoder has been built using the tool. Implementation of the design in FPGA has proven the capability of the tool in handling large and complex designs.

【 授权许可】

Unknown