Analytical memory bandwidth model for many-core processor based systems

IEICE Electronics Express

Eui-Young Chung¹  Woo-Cheol Cho²  Hyuk-Jun Lee² 

[1] School of Electrical and Electronic Engineering, Yonsei University;Dept. of Computer Science and Engineering, Sogang University

关键词: many-core;    cache miss;    memory bandwidth;    central limit theorem;   

DOI  :  10.1587/elex.9.1461

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)Many-core processor based systems gain popularity in high-performance parallel embedded applications. Estimating memory bandwidth requirement, i.e. external memory bandwidth, given various cache size for target parallel applications requires a prohibitively large simulation time. In this work, we propose an analytical model to quickly estimate the memory bandwidth for a given cache size and help exploring trade-offs between cache sizes and memory bandwidth requirement. We model the stochastic behavior of cache misses for a single cache as a random process. Using central limit theorems for identically or non-identically distributed random processes, we accurately estimate the collective cache misses from hundreds of processor cores and thus the total memory bandwidth requirement for the whole system. The results show that our model improves a speed of simulation time up to 200.4 times for 200 cores whereas its estimated results achieve less than 0.01% difference from the simulated ones for 200 cores in terms of accuracy.

【 授权许可】

Unknown