High-speed demonstration of low-power 1 k-bit shift-register memories using LR-biasing SFQ circuits

IEICE Electronics Express

Yuki Yamanashi¹  Nobuyuki Yoshikawa¹  Ryo Numaguchi¹  Toshihiro Takahashi¹ 

[1] Dept. of Electrical and Computer Engineering, Yokohama National University

关键词: SFQ circuits;    shift register;    memory;    superconducting integrated circuits;   

DOI  :  10.1587/elex.13.20160074

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(10)We designed a low-power shift-register memory using single-flux-quantum (SFQ) circuits for bit-serial SFQ microprocessors. In order to reduce the static power consumption of the SFQ memories, LR-biasing SFQ circuits were employed, where the resistance network for supplying the bias current is replaced with the inductance network with small resistance. We implemented a low-power 1 k-bit SFQ shift-register memory and confirmed its 30 GHz operation for all addresses. The power consumption was reduced to 26% of the conventional resistively biased SFQ memories.

【 授权许可】

Unknown