Timing margin enhancement technique for current mode interface

IEICE Electronics Express

Makoto Nagata¹  Takefumi Yoshikawa¹ 

[1] Graduate School of System Informatics, Kobe University

关键词: interface;    current mode;    low power;   

DOI  :  10.1587/elex.11.20140766

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(3)This paper presents a circuit technique to enhance a timing margin between internal data and clock by enlarging an eye opening of the internal data in a unique current mode transceiver [1]. This technique compensates a systematic timing offset of the internal data, which is caused by unbalanced transmission current. The test-chip exhibits 0.1UI (Unit Interval) improvement of the internal data eye opening without significant power penalty, and achieves stable data communication through 50% longer transmission lines compared to the previous work [1].

【 授权许可】

Unknown