Efficient implementation of FPGA based central pattern generator using distributed arithmetic

IEICE Electronics Express

Xiaojun Li¹  Lin Li¹ 

[1] Robotics Lab, Faculty of Mechanical Engineering and Automotives, South China University of Technology

关键词: central pattern generators (CPGs);    Field Programmable Gate Arrays (FPGAs);    look up tables (LUTs);    distributed-arithmetic (DA);   

DOI  :  10.1587/elex.8.1848

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)Cited-By(1)A scheme for efficient hardware implementation of central pattern generators (CPGs) on Field Programmable Gate Arrays (FPGAs) is proposed. A revised distributed-arithmetic (DA) algorithm is applied to the implementation to maximize the utilization of look up tables (LUTs) in FPGAs. The proposed scheme performances satisfactory experiment results which have correlation coefficients of 0.99 with simulation ones. In the mean time, it demonstrates 74% reduction in LUTs consumption, 75% in registers and 100% in embedded multipliers.

【 授权许可】

Unknown