A test pattern generation method with high compression ratio

IEICE Electronics Express

Feng Liang¹  Luwen Zhang¹  Shaochong Lei¹ 

[1] School of Electronic and Information Engineering, Xi'an Jiaotong University

关键词: test pattern generation;    test compression;    linear relation;   

DOI  :  10.1587/elex.8.1842

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(5)This paper proposes a test pattern generation and compression method to reduce test volume for VLSI testing. Unlike traditional approaches, the proposed scheme predefines linear relationships between vectors or within a vector of a test sequence firstly. Then, it determines test patterns by fault simulation. Therefore, patterns of a deterministic test set keep the predefined linear relationships, and can be highly compressed. Simulation results on ISCAS'89 benchmarks demonstrate that the proposed method can significantly reduce the data size with high fault coverage.

【 授权许可】

Unknown