期刊论文详细信息
IEICE Electronics Express | |
Implementation of high-speed SHA-1 architecture | |
Il-Hwan Park1  Kyoung-Rok Cho2  Je-Hoon Lee2  Eun-Hee Lee2  | |
[1] National Security Research Institute;BK21 Chungbuk Information Tech. Center, Chungbuk Nat'l University | |
关键词: cryptography; secure hash algorithm; hardware design; | |
DOI : 10.1587/elex.6.1174 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
References(6)Cited-By(5)This paper proposes a new SHA-1 architecture to exploit higher parallelism and to shorten the critical path for Hash operations. It enhances a performance without significant area penalty. We implemented the proposed SHA-1 architecture on FPGA that showed the maximum clock frequency of 118MHz allows a data throughput rate of 5.9Gbps. The throughput is about 26% higher, compared to other counterparts. It supports cryptography of high-speed multimedia data.
【 授权许可】
Unknown
【 预 览 】
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RO201911300656273ZK.pdf | 1897KB | download |