Reconfigured test architecture optimization for TSV-based three-dimensional SoCs

IEICE Electronics Express

Zhou Jiang²  Dong Xiang²  Kele Shen¹ 

[1] Department of Computer Science, Tsinghua University;School of Software, Tsinghua University

关键词: 3D SoC;    optimization;    DfT;    test access mechanism (TAM);    test time;   

DOI  :  10.1587/elex.11.20140661

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(9)The technology of three-dimensional (3D) SoCs is emerging as a promising approach for extending Moore’s Law. Managing test architecture design and optimization of 3D integration are crucial challenges. In this paper, we propose a reconfigured test architecture optimization for 3D SoCs, including a novel scheme to minimize the pre-bond test time and Known-Good Stack (KGS) test to guarantee the yield of 3D SoCs. Experimental results on ITC�?02 SoC benchmark circuits show that our scheme reduces the total test time by around 23% on average and nearly 30% in maximum compared with one baseline solution.

【 授权许可】

Unknown