Highly linear low voltage low power CMOS LNA

IEICE Electronics Express

Hooman Nabovati²  Negar Zoka³  Ehsan Kargaran²  Abbas Z. Kouzani¹  Khalil Mafinezhad² 

[1] School of Engineering, Deakin University;Department of Electrical Engineering Sadjad Institute for Higher Education;Department of Electrical Engineering, Ferdowsi University

关键词: low noise amplifier (LNA);    folded cascode;    high linear;    low power;    low voltage;    current reuse;   

DOI  :  10.1587/elex.10.20130557

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(10)A highly linear, low voltage, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique is presented in this paper. Parallel Inductor (PI) matching is used to increase LNA gain by 3dB at the desired frequency. The linear LNA was designed and simulated in a TSMC 0.18μm CMOS process at 5GHz frequency. By employing the proposed technique, the IIP3 is improved by 12dB in contrast to the conventional folded cascode LNA, reaching −1dBm without having any significant effect on the other LNA parameters such as gain, NF and also power consumption. The proposed LNA also delivers a voltage gain (S21) of 12.25dB with a noise figure of 3.5dB, while consuming only 1.28mW of DC power with a low supply voltage of 0.6V.

【 授权许可】

Unknown