Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications

IEICE Electronics Express

Hideo Sato¹  Sadahiko Miura²  Takahiro Hanyu¹  Masanori Natsui¹  Akira Mochizuki¹  Hideo Ohno¹  Hiroaki Honjo²  Tetsuo Endoh¹  Keizo Kinoshita¹  Shoji Ikeda¹  Daisuke Suzuki¹ 

[1] Center for Spintronics Integrated Systems, Tohoku University;Green Platform Research Laboratories, NEC Corporation

关键词: field-programmable gate array;    magnetic tunnel junction device;    nonvolatile logic-in-memory architecture;    power-gating;   

DOI  :  10.1587/elex.10.20130772

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(13)Cited-By(6)A nonvolatile field-programmable gate array (NVFPGA) test chip with 240 tiles (the basic components) in a 12 × 20 2D-array is fabricated by 90nm CMOS and 70nm magnetic tunnel junction (MTJ) technologies. Since not only circuit configuration data but also temporal data are still remained in the MTJ devices even when the power supply is cut off, standby power dissipation is completely eliminated by utilizing tile-level power gating. Power reduction is further accelerated by skipping wasted write operations of nonvolatile flip-flops (NVFFs) for storing temporal data when the temporal data and the stored one are the same. As a typical application, a motion-vector prediction function is implemented on the proposed NVFPGA, which results in a write power reduction of 77% compared to that of a conventional MTJ-based NVFPGA and a total power reduction of 70% compared to that of an SRAM-based FPGA.

【 授权许可】

Unknown