A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique

IEICE Electronics Express

M. Terada²  S. Okumura²  H. Kawaguchi²  S. Miyano³  M. Yoshimoto²  S. Yoshimoto²  T. Suzuki¹ 

[1] Panasonic Corporation;Depratment of Information science Kobe University;Semiconductor Technology Academic Research Center (STARC)

关键词: SRAM;    8T;    disturb;    half-select;   

DOI  :  10.1587/elex.9.1023

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the seven samples show that the proposed DW8T SRAM achieves a VDDmin of 600mV and improves the average VDDmin by 367mV compared to the conventional 8T SRAM. The measured leakage power can be reduced by 25%.

【 授权许可】

Unknown