A novel layout placement structure to mitigate the multi-bit-upset in 6T-SRAM cell

IEICE Electronics Express

Xu Hui¹  Zeng Yun¹ 

[1] School of Physics and Electronics, Hunan University

关键词: SRAM;    single error correction;    MBU;    layout structure;   

DOI  :  10.1587/elex.11.20140396

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(13)Cited-By(4)A novel layout structure for the typical 6T-SRAM cell is designed to mitigate the single-event induced MBU. And three-dimensional technology computer-aided design (TCAD) numerical simulation is used to evaluate the MBU hardening performance of this novel layout structure. Compared to other layout structures, our proposed layout can effectively attenuate the single-event induced MBU in typical 6T-SRAM with little area and power penalty.

【 授权许可】

Unknown