A 6-bit 1GS/s DAC using an area efficient switching scheme for gradient-error tolerance

IEICE Electronics Express

Yuhua Cheng¹  Hui Wang¹  Tao Wang¹  Yufeng Yao¹  Haonan Wang¹ 

[1] Shanghai Research Institute of Microelectronics (SHRIME), Peking University

关键词: DAC;    switching scheme;    gradient error;   

DOI  :  10.1587/elex.10.20130328

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(5)Cited-By(1)This paper presents a 6-bit current-steering DAC fabricated in 65nm digital CMOS process. In order to compensate for the systematic errors on the current sources, a novel switching scheme is proposed which can theoretically cancel out linear and quadratic gradient errors. Its implementation only requires reasonable number of current sources without increasing in the design complexity. The measured DNL and INL are 0.012LSB and 0.023LSB respectively. At the sampling rate of 1GS/s, 5.9bit ENOB and 51.4dB SFDR at Nyquist frequency are achieved.

【 授权许可】

Unknown