A new 6-T multiplexer based full-adder for low power and leakage current optimization

IEICE Electronics Express

C. Senthilpari¹  T. S. Lim¹  P. Velrajkumar¹  G. Ramana Murthy¹ 

[1] Faculty of Engineering and Technology, Multimedia University

关键词: full-adder;    low-power;    multiplexing;    Pass Transistor Logic (PTL);    temperature coefficient;    high-speed;   

DOI  :  10.1587/elex.9.1434

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)Cited-By(1)Addition is a fundamental arithmetic operation which is used extensively in many very large-scale integration (VLSI) systems such as application-specific digital signal processing (DSP) and microprocessors. An adder determines the overall performance of the circuits in most of those systems. In this paper a 1-bit full adder cell which uses only six transistors has been proposed. In this design, three multiplexers and one inverter are used to minimize the transistor count and reduce power consumption. The power dissipation, propagation delay and power-delay product (PDP) are analyzed and compared with the existing adders using BSIM4 at 90nm feature size. The results show that the proposed adder has both lower power consumption and low PDP value. The proposed full adder clearly outperforms other existing adders in its temperature sustainability behavior versus power dissipation, leakage current parameters. The low power and low transistor count makes the proposed 6T full adder cell a candidate for power-efficient applications.

【 授权许可】

Unknown