IEICE Electronics Express | |
A parallel power amplifier with load impedance transformation for optimized low power performance | |
Jongsoo Lee1  Geunyong Lee1  | |
[1] Dept. Information and Communications, Gwangju Institute of Science and Technology | |
关键词: chain matching networks; load impedance transformation; low power efficiency and linearity; parallel power amplifier; WCDMA; | |
DOI : 10.1587/elex.8.956 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
References(4)This paper presents analytic expressions for T-type chain matching network synthesis of the power amplifier (PA) to enhance the performance at low output powers via a load impedance adjustment. Here, a parallel power amplifier for WCDMA B1 (1920-1980MHz) based on an InGaP/GaAs hetero-junction bipolar transistor (HBT) is utilized, which has a fully integrated matching network on a printed circuit board (PCB). As a result, the power amplifier shows a 38.7% power added efficiency (PAE), and a -37dBc adjacent channel leakage power ratio (ACLR) at 27.5dBm output during high power mode operation, and 17.6% PAE with a 22mA quiescent current and a -40.7dBc at a back-off output power of 17dBm during low power mode.
【 授权许可】
Unknown
【 预 览 】
Files | Size | Format | View |
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RO201911300333287ZK.pdf | 407KB | download |