A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin

IEICE Electronics Express

Hans Jürgen Mattausch¹  Koh Johguchi¹  Ken-ichi Aoyama¹  Yuya Mukuda¹  Tetsushi Koide¹ 

[1] Research Center for Nanodevices and Systems, Hiroshima University

关键词: SRAM;    multi-port memory;    distributed crossbar;    multi-stage sensing;   

DOI  :  10.1587/elex.4.21

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(6)Cited-By(2)A 90nm CMOS, 64Kbit, 1.16GHz, 16 port SRAM with multi-bank architecture realizing 590Gbps random access bandwidth, 41mW power dissipation at 1GHz and 0.91mm2 (13.9µm2/bit) area consumption is reported. Compared to conventional 16 port SRAM data, area and power consumption are reduced by factors 16 and 5, respectively, while maximum clock frequency is about a factor 2 higher.

【 授权许可】

Unknown