A new five-moduli set for efficient hardware implementation of the reverse converter

IEICE Electronics Express

Amir Sabbagh Molahosseini¹  Chitra Dadkhah²  Keivan Navi³ 

[1] Department of Computer Engineering, Science and Research Branch, Islamic Azad University;Department of Electrical Engineering, K. N. Toosi University of Technology;Department of Electrical and Computer Engineering, Shahid Beheshti University

关键词: reverse converter;    residue arithmetic;    VLSI architectures;   

DOI  :  10.1587/elex.6.1006

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)Cited-By(6)In this paper, we propose an efficient hardware implementation of the reverse converter for the new five-moduli set {2n, 2n/2-1, 2n/2+1, 2n+1, 22n-1-1} for even n. The converter has a two-level architecture, and is based on combination of new Chinese remainder theorem 1 (New CRT-I) and mixed-radix conversion (MRC). The presented reverse converter has lower hardware requirements, and results in a significant reduction in the conversion delay, compared to the reverse converter of the latest introduced five-moduli set {2n-1, 2n, 2n+1, 2n-1-1, 2n+1-1} that has the same dynamic range as the proposed five-moduli set.

【 授权许可】

Unknown