Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance

IEICE Electronics Express

Min-Chul Sun³  In Man Kang¹  James S. Harris, Jr.²  Seongjae Cho²  Byung-Gook Park³  Hyungjin Kim³ 

[1] School of Electronics Engineering, Kyungpook National University;Department of Electrical Engineering, Stanford University;Inter-university Semiconductor Research Center (ISRC) and Department of Electrical Engineering and Computer Science, Seoul National University

关键词: methodology;    channel length limit;    tunneling field-effect transistor;    silicon nanowire;    evaluating function;    tunneling-predominance;   

DOI  :  10.1587/elex.9.828

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)Cited-By(1)In this work, a strategic methodology to determine the channel length limit for the predominance of tunneling mechanism in the operation of a tunneling field-effect transistor (TFET) is suggested and validated for silicon (Si) nanowire TFET device. For quantitative analyses that can be graphitized as a function of channel length, a set of evaluating functions were defined and properly applied. Based on the suggested methodology, the upper limit for keeping the Si TFET under the tunneling-predominant operation turned out to be approximately 65nm in a nanowire structure.

【 授权许可】

Unknown