A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface

IEICE Electronics Express

Sang Joon Hwang¹  Young Hyun Jun²  Man Young Sung¹ 

[1]Dept. of Electrical Engineering, Korea University

[2]DRAM Design Team, Memory Division, Samsung Electronics Co., Ltd.

关键词: GDDR3 SDRAM;    termination;    signal integrity;   

DOI  :  10.1587/elex.5.446

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(4)The keys to good signal integrity in a Graphic DDR3 (GDDR3) SDRAM interface for a bandwidth up to 1.4Gbps/pin are the minimization of input/output pin capacitance and the accurate control of the output data skew. The proposed pre-emphasis output buffer control scheme provides output data skew minimization without an increase of input/output pin capacitance. Compared to the conventional scheme, the output data aperture window of proposed scheme has increased by 18% and the data output skew has decreased by 48%.

【 授权许可】

Unknown