A 600kHz to 1.2GHz all-digital delay-locked loop in 65nm CMOS technology

IEICE Electronics Express

Ching-Che Chung²  Chia-Lin Chang²  Duo Sheng¹ 

[1] Department of Electrical Engineering, Fu Jen Catholic University;Department of Computer Science & Information Engineering, National Chung-Cheng University

关键词: digital delay-locked loop;    delay line;    delay circuit;    clocks;    synchronization;    jitter;   

DOI  :  10.1587/elex.8.518

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)This paper presents an ultra-wide-range all-digital delay-locked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor's leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600kHz to 1.2GHz in the typical case. The power consumption of the DLL is 2.6mW at 1.2GHz and 0.366mW at 600kHz with 1.0V power supply. The measured r.m.s jitter and peak-to-peak jitter at 1.2GHz are 3.38ps and 39.29ps, respectively.

【 授权许可】

Unknown