A 0.6-V 1.6-GHz 8-phase all digital PLL using multi-phase based TDC

IEICE Electronics Express

Hong-Yi Huang³  Kuo-Hsing Cheng²  Chang-Chien Hu²  Jen-Chieh Liu¹  Yo-Hao Tu² 

[1] Department of Electrical Engineering, National United University;Department of Electrical Engineering, National Central University;Graduate Institute of Electrical Engineering, National Taipei University

关键词: all-digital phase-locked loop (ADPLL);    digital controlled oscillator (DCO);    time-to-digital converter (TDC);    time amplifier (TA);    low supply voltage;    multi-phase outputs;   

DOI  :  10.1587/elex.12.20150950

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(15)This paper proposes an 8-phase all-digital phase-locked loop (ADPLL) for a low supply voltage application. The proposed multi-phase digitally controlled oscillator (MP-DCO) employs two sub-feedback loops at high operational frequencies. The proposed multi-phase-based time-to-digital converter (MP-TDC) uses the multi-phase scheme, which reduces its area, and uses a time amplifier to extend the timing resolution. With a low supply voltage, the DCO and the sense-amplifier based delay flip-flop (SA-DFF) use bulk-controlled techniques to improve the performance at high operational frequencies and setup/hold times, respectively. When the ADPLL output is 1.6 GHz at 0.6 V, the RMS and peak-to-peak jitters are 3.8 ps and 33.7 ps, respectively. The power consumption and core area are 9.1 mW at 1.6 GHz and 0.036 mm2 in a 90 nm CMOS process, respectively. Thus, this clock generator is useful for low power systems.

【 授权许可】

Unknown