A 1.0-V 10-b 30-MS/s 3.4-mW rail-to-rail pipelined ADC using a new front-end MDAC

IEICE Electronics Express

Hiroshi Ando¹  Kunihiko Gotoh²  Atsushi Iwata¹ 

[1] Graduate School of Advanced Sciences of Matter, Hiroshima University;System LSI Development Lab, Fujitsu Laboratories Ltd.

关键词: pipeline ADC;    MDAC;    op-amp;    low-voltage;    low-power;   

DOI  :  10.1587/elex.6.198

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

References(7)Cited-By(1)This paper describes a low-voltage design for a pipelined ADC that can operate in a 2.0-Vpp full-swing input range at a 1.0-V supply. To enlarge the input range of an ADC and maintain the output range of its op-amps, we propose a new front-end 2b-MDAC with S/H that can reduce the output ranges of all MDACs by 50% compared to the ADC's input. We designed a 10-b pipelined ADC with the proposed front-end MDAC using a 90-nm CMOS process. The ADC achieved 2.0-Vpp rail-to-rail operation at only a 1-V supply and a 57.5-dB SNDR with only 3.4mW at 30MS/s despite using conventional folded-cascode op-amps.

【 授权许可】

Unknown