A novel high performance 3×VDD-tolerant ESD detection circuit in advanced CMOS process

IEICE Electronics Express

Xi Li¹  Houpeng Chen¹  Jie Miao²  Yu Lei²  Xiaoyun Li³  Qian Wang³  Zhitang Song³ 

[1] Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences;University of Chinese Academy of Sciences;State Key Laboratory of Functional Materials for Informatics

关键词: electrostatic discharge (ESD);    mixed-voltage I/O;    high trigger current;    detection circuit;    28 nm HKMG CMOS process;   

DOI  :  10.1587/elex.14.20170899

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

A novel high performance 3×VDD-tolerant electrostatic discharging (ESD) detection circuit using only 1×VDD devices was presented in a 28 nm 1.8 V high-k metal-gate (HKMG) CMOS technology. A sub-path and an enhanced path were adopted in this novel design to increase its trigger current. Two small-sized PMOS transistors were employed to protect this circuit out of gate-oxide reliability issues under normal operating conditions. And there is only one capacitor in our novel circuit to maintain a small layout area. Under the ESD stress events, spectre-simulation results show that the trigger current of our proposed circuit can reach 36.4 mA. And its leakage current is only 2.8 nA at 27°C, 243 nA at 120°C under normal operating conditions.

【 授权许可】

CC BY