Enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration

IEICE Electronics Express

Yu Lei¹  Xi Li¹  Xi Fan¹  Zhen Tian¹  Jiajun Hu¹  Xiaoyun Li¹  Houpeng Chen¹  Qi Zhang¹  Qian Wang¹  Zhitang Song¹ 

[1] State Key Laboratory of Functional Materials for Informatics (Shanghai Institute of Microsystem and Information Technology), Chinese Academy of Sciences

关键词: electrostatic discharge (ESD);    power clamp;    mixed-voltage I/O;    high discharge current;    SOI CMOS process;    28 nm high-k CMOS process;   

DOI  :  10.1587/elex.14.20160901

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

An enhanced 3 × VDD-tolerant ESD clamp circuit with stacked configuration was presented.Four transistors were added in this design to transfer bias voltages or ESD voltages. This circuit was simulated in 0.18 µm silicon-on-insulator (SOI) CMOS process and 28 nm HKMG CMOS technology. Spectre-simulation results showed that the ESD discharge current is increased by 2 times and the discharge current is decreased to nA magnitudes compared to the conventional circuit.

【 授权许可】

CC BY