IEICE Electronics Express | |
A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs | |
SW Han1  Jongsun Kim1  | |
[1] Electronic and Electrical Engineering, Hongik University | |
关键词: duty-cycle corrector; LPDDR3; LPDDR4; SDRAM; memory; DRAM; | |
DOI : 10.1587/elex.15.20180156 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
A new low-power, fast-lock duty-cycle corrector (DCC) circuit with a digital duty-cycle adjuster (DCA) for mobile LPDDR3/LPDDR4 DRAMs is presented. The proposed DCC utilizes a digital feedback delay element (DFDE) to achieve wide duty-cycle correction and operating frequency ranges with low power consumption and fast lock capability. To obtain fast locking time and high duty-cycle correction accuracy, a 6-bit successive approximation register (SAR) controller utilizing a hybrid search algorithm is adopted. The measured duty-cycle error is less than ±0.85% over a 30â70% input duty-cycle range at 0.2â1.5 GHz. The DCC, which is fabricated in a 0.13-µm CMOS process, dissipates only 1.9 mW at 1 GHz and occupies an area of 0.036 mm2.
【 授权许可】
CC BY
【 预 览 】
Files | Size | Format | View |
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RO201902197510454ZK.pdf | 3274KB | download |