IEICE Electronics Express | |
A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs | |
Junsub Yoon1  Jongsun Kim1  Seo Weon Heo1  | |
[1] Electronic and Electrical Engineering, Hongik University | |
关键词: delay-locked loop; DDR3; DDR4; SDRAM; harmonic-free; DLL; | |
DOI : 10.1587/elex.13.20161020 | |
学科分类:电子、光学、磁材料 | |
来源: Denshi Jouhou Tsuushin Gakkai | |
【 摘 要 】
A new digital delay-locked loop (DLL) for DDR3/DDR4 SDRAM is presented. The proposed digital DLL employs a new noise-tolerant triple (MSB-interval + binary + sequential) search algorithm for implementing a harmonic-free, fast-locking capability while retaining low jitter, low power performance, and a wide operating frequency range. The proposed DLL with duty-cycle correction is designed using a 38-nm CMOS process and occupies an active area of just 0.02 mm2. The DLL operates over a frequency range of 0.3â2.0 GHz and achieves a peak-to-peak jitter of 7.78 ps and dissipates 3.48 mW from a 1.1 V supply at 1 GHz.
【 授权许可】
CC BY
【 预 览 】
Files | Size | Format | View |
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RO201902193330227ZK.pdf | 2942KB | download |