Analytical inverter chain’s delay and its variation model for sub-threshold circuits

IEICE Electronics Express

Wei Ge¹  Jingjing Guo¹  Min Wang¹  Jianxin Nie¹  Jun Yang¹  Jizhe Zhu¹  Xinning Liu¹ 

[1] National ASIC System Engineering Technology Research Center, Southeast University

关键词: sub-threshold circuit;    lognormal distribution;    delay model;    variation analysis;   

DOI  :  10.1587/elex.14.20170390

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

Sub-threshold circuit is a promising circuit design style for IoT application. This paper concentrated on the delay model based on the transient current model in the sub-threshold region. In order to deduce the path delay model, two ways are adopted, which are the coupling capacitance equivalence and the output waveform equivalence. The distribution of path delays is rigidly proven to be lognormal distribution in the sub-threshold region. Considering different supply voltages, cell driven strengths and load capacitances, the proposed model is also validated by Monte Carlo Spice simulation under SMIC 40 nm CMOS process. Experiments show that proposed model agrees with MC simulation results with error 0.448% under the condition of 0.4 V and 99.7% probability, which proves the feasibility of the model.

【 授权许可】

CC BY