LDO regulator with high power supply rejection at 10 MHz

IEICE Electronics Express

Jeongjin Roh¹  Khurram Javed¹ 

[1] Department of Communication and Electronics Engineering, Hanyang University

关键词: low-dropout regulator;    power supply rejection;    negative capacitance;   

DOI  :  10.1587/elex.13.20160665

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

A new high-frequency power supply rejection (PSR) improvement technique is presented for a low-dropout (LDO) regulator. The proposed technique utilizes a negative capacitance at the gate of the power transistor to enhance the PSR at high frequencies by neutralizing the effect of parasitic capacitances. The simulation results show that the LDO is able to achieve a PSR of −67.9 dB at 10 MHz.

【 授权许可】

CC BY