A novel power-efficient IC test scheme

IEICE Electronics Express

Ding Deng¹  Yang Guo¹  Xiaowen Chen¹ 

[1] College of Computer, National University of Defense Technology

关键词: low power;    scan test;    parallel;   

DOI  :  10.1587/elex.14.20170462

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

A novel power-efficient IC test scheme is proposed, containing parallel test application (PTA) architecture and its procedure. PTA parallelizes the stimuli assignments and the vectors can be observed immediately once applied, which assures the shift safety timely and hence only logic test is required. The procedure contains two phases for each pattern. In shift phase, each clock chain is activated in turn and the vectors are assigned in parallel. In capture phase, all chains are captured simultaneously. Experimental results demonstrate that, compared with the traditional serial scan scheme, the proposal reduces average power by 88.48% and peak power by 53.36%.

【 授权许可】

CC BY