A lightweight implementation of the Tav-128 hash function

IEICE Electronics Express

Enrique San Millan¹  Pedro Peris Lopez²  Honorio Martin³  Juan E. Tapiador³ 

[1] Department of Computer Science, Aalto University;Department of Computer Science, University Carlos III of Madrid;Department of Electronic Technology, University Carlos III of Madrid

关键词: hardware implementation;    hash function;    ASIC;    FPGA;   

DOI  :  10.1587/elex.14.20161255

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

In this article we discuss the hardware implementation of a lightweight hash function, named Tav-128 [1], which was purposely designed for constrained devices such as low-cost RFID tags. In the original paper, the authors only provide an estimation of the hardware complexity. Motivated for this, we describe both an ASIC and an FPGA-based implementation of the aforementioned cryptographic primitive, and examine the performance of three architectures optimizing different criteria area, throughput, and a trade-off between both of them.

【 授权许可】

CC BY