A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video

IEICE Electronics Express

Masahiko Yoshimoto¹  Toshio Goto²  Hiroshi Kawaguchi³  Shintaro Izumi³  Taisuke Kodama³  Koichi Kajihara³  Go Matsukawa³  Yuri Nishizumi³  Chikako Nakanishi⁴  Takeo Kato⁵ 

[1] D Labs., Inc;Electronics Advanced Development Department, Toyota Motor Corporation;Graduate School of System Informatics, Kobe University;Osaka Institute of Technology;Toyota Central R&

关键词: Sparse FIND;    object recognition;    HDTV;    low-power;    VLSI;   

DOI  :  10.1587/elex.14.20170668

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper describes a low-power object recognition processor VLSI for HDTV resolution video at 60 frames per second (fps) using an object recognition algorithm with Sparse FIND features. The VLSI processor features two-stage feature extraction processing by HOG and Sparse FIND, a highly parallel classification in the support vector machine (SVM), and a block-parallel processing for RAM access cycle reduction. Compared to the accuracy by the original Sparse FIND algorithm, the two-stage object detection demonstrates insignificant accuracy degradation. Using this architectural design, a 60 fps performance for object recognition of HDTV resolution video was attained at an operating frequency of 130 MHz. This 3.35 × 3.35 mm2 chip, designed with 40 nm CMOS technology, contains 8.22 M gates and 5 Mb SRAM in the chip of 3.35 × 3.35 mm2. The simulated power consumption at 133 MHz were 528 mW and 702 mW at the slow process condition (SS, 0.81 V, −40°C) and typical process condition (TT, 0.9 V, 25°C), respectively.

【 授权许可】

CC BY