Design and FPGA prototyping of a H: 264/AVC main profile decoder for HDTV

Journal of the Brazilian Computer Society

Agostini, Luciano V.¹  Zatt, Bruno¹  Pinto, Ana Cristina M.¹  Bampi, Sergio¹  Federal University of Rio Grande do Sul, Porto Alegre, BRAZIL¹  Azevedo Filho, Arnaldo P.¹  Porto, Roger Endrigo¹  Rosa, Vagner S.¹  Staehler, Wagston T.¹  Susin, Altamiro A.¹  Federal University of Pelotas, Pelotas, BRAZIL¹ 

关键词: Video Coding;    H.264/AVC Decoder;    Digital Television;    HDTV;    VLSI Architectures;    FPGA Prototping.;   

DOI  :  10.1590/S0104-65002007000100004

学科分类：农业科学（综合）

来源: Springer U K

【 摘 要 】

This paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.

【 授权许可】

Unknown