A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler

IEICE Electronics Express

Fengqi Yu¹  Wenjian Jiang¹  Qinjin Huang¹ 

[1] Shenzhen Institutes of Advanced Technology, Chinese Academy of Science

关键词: dual-modulus prescaler;    TSPC;    high-speed;    low-power;   

DOI  :  10.1587/elex.13.20160446

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

A novel low-power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. Compared with the conventional topologies, one of the precharge stages in the TSPC flip-flops is eliminated, and the number of switching stages is reduced to 5. The prescaler is implemented in a standard 0.18-µm CMOS process. It achieves the maximum operating frequency of 5.7 GHz with a measured power consumption of 0.95 mW and 0.98 mW in divide-by-3 mode and divide-by-2 mode, respectively, when operated at 1.5-V power supply.

【 授权许可】

CC BY