Multi-core architecture with asynchronous clocks to prevent power analysis attacks

IEICE Electronics Express

Xiaoyun Li¹  Zhitang Song¹  Yuan Du²  Weiliang Jing²  Bomy Chen²  Zhenhua Li³  Yong Ye³ 

[1] Shanghai Xinchu Integrated Circuit Incorporation;State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences;University of Chinese Academy of Sciences

关键词: cryptographic algorithm;    power analysis attacks;    security;    multi-core;   

DOI  :  10.1587/elex.14.20161220

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

This paper proposes a multi-core architecture with asynchronous clocks to prevent power analysis attacks for the first time. The multi cores normally execute different tasks with default clocks, but will execute the cryptographic algorithm together with asynchronous clocks to foil the side channel attacks. The cryptographic algorithm is split into multi parts, each of which is executed simultaneously by one core. Security analysis and simulation results show that the differential power analysis (DPA) attack and correlation power analysis (CPA) attack fail on data encryption standard (DES) and advanced encryption standard (AES) with the proposed architecture.

【 授权许可】

CC BY