Efficient AES cipher on coarse-grained reconfigurable architecture

IEICE Electronics Express

Chao Wang¹  Peng Cao¹  Jun Yang¹ 

[1] National ASIC System Engineering Research Center, Southeast University

关键词: coarse-grained reconfigurable architecture (CGRA);    advanced encryption standard (AES);    mapping scheme;   

DOI  :  10.1587/elex.14.20170449

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

By exploring the mapping schemes with dataflow graph (DFG) transformation and different granularity of task-level parallelism, we presented various AES implementations on a coarse grained reconfigurable architecture (CGRA) to meet the requirements raging from high performance to low power. In comparison with published AES cipher implementations on programable processors, our AES cipher has 14.7∼121.4× higher energy efficiency. Moreover, the design shows the advantage over other CGRAs with 1.3∼4.5× energy efficiency improvement.

【 授权许可】

CC BY