A 19-bit column-parallel folding-integration/cyclic cascaded ADC with a pre-charging technique for CMOS image sensors

IEICE Electronics Express

Keita Yasutomi¹  Shoji Kawahito¹  Tongxi Wang¹  Min-Woong Seo¹ 

[1] Research Institute of Electronics, Shizuoka University

关键词: CMOS image sensors;    column-parallel ADCs;    folding-integration ADC;    cyclic ADC;    high-resolution;    pre-charge technique;   

DOI  :  10.1587/elex.14.20161199

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

A high-resolution column-parallel folding-integration/cyclic cascaded (FICC) ADC with a pre-charging technique for CMOS image sensors is presented in this paper. To achieve high-resolution data conversion with multiple sampling, a pre-charging technique is applied to the sampling circuits of the FICC ADC to reduce the influence of incomplete discharging of historical previous samples. This technique effectively reduces differential nonlinearity of the ADC. The prototype chip with 1504 columns FICC ADC array has been implemented and fabricated in 110 nm CMOS technology. The measured DNL of column-parallel FICC ADC with 128 times multiple sampling is −1/4.73 LSBs in sampling speed of 13 KS/s and 19-bit resolution.

【 授权许可】

CC BY