Efficient bit-parallel systolic architecture for multiplication and squaring over GF(2m)

IEICE Electronics Express

Seung-Hoon Kim¹  Kee-Won Kim¹ 

[1] Department of Applied Computer Engineering, Dankook University

关键词: finite field;    modular multiplication;    squaring;    systolic array;    cryptography;   

DOI  :  10.1587/elex.14.20171195

学科分类：电子、光学、磁材料

来源: Denshi Jouhou Tsuushin Gakkai

【 摘 要 】

In this letter, we propose a parallel-in parallel-out systolic array for concurrently computing multiplication and squaring over GF(2m). For m ≥ 400, the proposed bit-parallel systolic array can save about 50% time complexity as compared to the corresponding existing structure. The proposed array can be used as a core circuit for various applications. Also our architecture is well suited to VLSI implementation as well.

【 授权许可】

CC BY