Design and Implementation of Unified Hardware for 128-Bit Block Ciphers ARIA and AES

ETRI Journal

关键词: resource sharing;    hardware architecture;    AES;    ARIA;   

Others  :  1185498
DOI  :  10.4218/etrij.07.0207.0077

【 摘 要 】

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

   

【 参考文献 】

• [1]FIPS pub. 197: Specification for the AES, Nov. 2001, available at: http://crsc.nist.gov/publications/fips/fips197/fips-197/pdf.
• [2]NSRI: Specification of ARIA, available at: http://www.nsri.re.kr/ ARIA/doc/ARIA-specification-e.pdf.
• [3]PKCS#11 v2.20 Amendment 3 Rev. 1: Additional PKCS#11 Mechanisms, available at: ftp://ftp.rsasecurity.com/pub/pkcs/pkcs-11/ v2-20/pkcs-11v2-20a3.pdf.
• [4]A. Satoh, S. Morioka, K. Takano, and Seiji Munetoh, "A Compact Rijndael Hardware Architecture with S-Box Optimization," ASIACRYPT ’01, Springer-Verlag, 2001, pp. 239-254.
• [5]A. Satoh and S. Morioka, "Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia," CHES, 2003, pp. 304-318.