A Viterbi Decoder with Efficient Memory Management

ETRI Journal

关键词: VLSI;    memory management;    Viterbi decoder;   

Others  :  1185178
DOI  :  10.4218/etrij.04.0303.0009

【 摘 要 】

This paper proposes a new architecture for a Viterbidecoder with an efficient memory management scheme.The trace-back operation is eliminated in the architectureand the memory storing intermediate decision informationcan be removed. The elimination of the trace-backoperation also reduces the number of operation cyclesneeded to determine decision bits. The memory size of theproposed scheme is reduced to 1/(5×constraint length) ofthat of the register exchange scheme, and the throughput isincreased up to twice that of the trace-back scheme. AViterbi decoder complying with the IS-95 reverse linkspecification is designed to verify the proposed architecture.The decoder has a code rate of 1/3, a constraint length of 9,and a trace-forward depth of 45.

   

【 参考文献 】

• [1]G. Forney, "Convolutional Codes II. Maximum-Likelihood Decoding," Information and Control, vol. 25, no. 3, July 1974, pp. 222-266.
• [2]K. Hu, W. Lin, and M. Caldwell, "A Viterbi Decoder Memory Management System Using Forward Traceback and All-Path Traceback," Proc. of the IEEE 1999 Int’l Conf. Consumer Electronics, 1999, pp. 68-69.
• [3]Heinrich Meyr, Marc Moenenclaey, and Stefan A. Fechtel, Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing, Wiley-Interscience, 1997.
• [4]Jens Sparso, Henrik N. Jorgensen, Erik Paaske, Steen Pendersen, and Thomas Rubner-Petersen, "An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type Structures," IEEE J. Solid-State Circuit, vol. 26, no. 2, F
• [5]Shu Lin and Daniel J. Costello Jr, Error Control Coding: Fundamentals and Applications, Prentice Hall, 1983.
• [6]J.L. Heller and I.W. Jacobs, "Viterbi Decoding for Satellite and Space Communication," IEEE Trans. Commun. COM19, no. 5, Oct. 1971, pp. 835-848.
• [7]Peter J. Black and Teresa H.-Y. Meng, "A 1-Gb/s, Four-State, Sliding Block Viterbi? Decoder," IEEE J. Solid-State Circuits, vol. 32, no. 6, June 1997, pp. 797-805.