Design and Implementation of Viterbi Decoder Using VHDL

3rd International Conference on Communication Systems

无线电电子学

Thakur, Akash^1 ; Chattopadhyay, Manju K^1

VLSI Design and Embedded System Lab, School of Electronics, Devi Ahilya University, Indore, India^1

关键词: ACSU;    Constraint lengths;    Conventional methods;    Convolutional encoders;    Design and implementations;    Digital designs;    Maximum frequency;    Viterbi decoder;   

Others  :  https://iopscience.iop.org/article/10.1088/1757-899X/331/1/012009/pdf
DOI  :  10.1088/1757-899X/331/1/012009

来源: IOP

【 摘 要 】

A digital design conversion of Viterbi decoder for 1/2 rate convolutional encoder with constraint length k = 3 is presented in this paper. The design is coded with the help of VHDL, simulated and synthesized using XILINX ISE 14.7. Synthesis results show a maximum frequency of operation for the design is 100.725 MHz. The requirement of memory is less as compared to conventional method.