ETRI Journal | |
Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication | |
关键词: interface schemes; chip-to-chip communication; Signaling; | |
Others : 1185310 DOI : 10.4218/etrij.05.0104.0113 |
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【 摘 要 】
In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 μm dual gate oxide CMOS technology.
【 授权许可】
【 预 览 】
Files | Size | Format | View |
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20150520110215431.pdf | 1481KB | download |
【 参考文献 】
- [1]Cangsang Zhao and Uddalak Bhattacharya, "An 18-Mb, 12.3 GB/s CMOS Pipeline-Burst Cache SRAM with 1.54 Gb/s/pin," IEEE J. Solid-State Circuits, vol. 34, Nov. 1999, pp. 1564-1570.
- [2]C.K.K. Yang et al., "A 0.8 um CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links," IEEE J. Solid-State Circuits, vol.31, Dec. 1996, pp. 2015-2023.
- [3]Y.S Yang et al, "A Serial Input/Output Circuit with 8 bit and 16 bit Selection Modes," ETRI J., vol.24, no.6, Dec. 2002, pp. 462-464.
- [4]S.I. Yoon et al., "Modeling of Multi-Level Interconnects for Full-Chip Simulation," Journal of the Korean Physical Society, vol. 40, no. 4, Apr. 2002, pp. 742-748.
- [5]Y.J. Park et al., "Output-Buffer-Delay Modeling Circuit for a High-Speed Data Interface," Journal of the Korean Physical Society, vol. 40, no. 4, Apr. 2002, pp. 709-711.
- [6]Chien-Cheng Yu, Wei-Ping Wang, and Bin-Da Liu, "A New Level Converter for Low-Power Applications," Circuits and Systems, 2001, ISCAS 2001, The 2001 IEEE Int’l Symp., vol. 1, pp. 113-116.
- [7]G.J. Ahn and D.K. Jeong et al., "A 2-Gbaud 0.7-V Swing Voltage Mode Driver and On-Chip Terminator for High Speed NRZ Data Transmission," IEEE J. Solid-State Circuits, vol. 35, June 2000, pp. 915-918.
- [8]H. Muljono et al., "A 400 MT/s 6.4 GB/s Multiprocessor Buf Interface," ISSCC 2003, vol. 1, pp. 338-339.
- [9]H. Djahanshhi et al., "Gigabit-Per-Second, ECL-Compatible I/O Interface in 0.35-um CMOS," IEEE J. Solid-State Circuits, vol. 34, Aug. 1999, pp. 1074-1083.