Voltage-Mode 1.5 Gbps Interface Circuits for Chip-to-Chip Communication

ETRI Journal

关键词: interface schemes;    chip-to-chip communication;    Signaling;   

Others  :  1185310
DOI  :  10.4218/etrij.05.0104.0113

【 摘 要 】

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 μm dual gate oxide CMOS technology.

   

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