An Experimental 0.8 V 256-kbit SRAM Macro with Boosted Cell Array Scheme

ETRI Journal

关键词: static noise margin;    booster;    memory;    SRAM;   

Others  :  1185535
DOI  :  10.4218/etrij.07.0106.0298

【 摘 要 】

This work presents a low-voltage static random access memory (SRAM) technique based on a dual-boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read-out current. A 0.18 µm CMOS 256-kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 µW/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.

   

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