A Two-Stage Radix-4 Viterbi Decoder for Multiband OFDM UWB Systems

ETRI Journal

关键词: MB-OFDM;    UWB;    radix-4;    Viterbi decoder;   

Others  :  1185623
DOI  :  10.4218/etrij.08.0208.0196

【 摘 要 】

This letter presents a power efficient 64-state Viterbi decoder (VD) employing a two-stage radix-4 add-compare-select architecture. A class of VD architectures is implemented, and their hardware complexity, maximum operating speed, and power consumption are compared. Implementation results show that the proposed VD architecture is suitable for multiband orthogonal frequency-division multiplexing (MB-OFDM) ultra-wideband (UWB) systems, which can support the data rate of 480 Mbps even when implemented using 0.18-µm CMOS technology.

   

【 参考文献 】

• [1]W. Abbott et al., "Multiband OFDM Physical Layer Specification, Version 1.2 (draft)," WiMedia Alliance, Feb. 2007.
• [2]C.W. Kim, S.S. Choi, and S.G. Lee, "A CMOS Frequency Synthesizer Block for MB-OFDM UWB Systems," ETRI Journal, vol. 29, no. 4, Aug. 2007, pp. 437-444.
• [3]K.M. Kang and S.S. Choi, "Initial Timing Acquisition for Binary Phase-Shift Keying Direct Sequence Ultra-Wideband Transmission," ETRI Journal, vol. 30, no. 4, Aug. 2008, pp. 495-505.
• [4]G. Fettweis and H. Meyr, "High-Rate Viterbi Processor: A Systolic Array Solution," IEEE J. Sel. Areas Comm., vol. 8, no. 8, Oct. 1990, pp. 1520-1534.
• [5]K.K. Parhi, "An Improved Pipelined MSB-First Add-Compare Select Unit Structure for Viterbi Decoders," IEEE Trans. Circuits and Systems I, vol. 51, no. 3, Mar. 2004, pp. 504-511.
• [6]P.J. Black and T.H.-Y. Meng, "A 1-Gb/s, Four-State, Sliding Block Viterbi Decoder," IEEE J. Solid-State Circuits, vol. 32, no. 6, June 1997, pp. 797-805.
• [7]C.B. Shung et al., "VLSI Architectures for Metric Normalization in the Viterbi Algorithm," Proc. ICC, vol. 4, Apr. 1990, pp. 1723-1728.
• [8]G. Feygin and P.G. Gulak, "Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi Decoders," IEEE Trans. Comm., vol. 41, no. 3, Mar. 1993, pp. 425-429.