A Die-Selection Method Using Search-Space Conditions for Yield Enhancement in 3D Memory

ETRI Journal

关键词: die-selection method;    inter-die redundancy;    3D memory stacking;    3D memory;    Yield enhancement;   

Others  :  1186024
DOI  :  10.4218/etrij.11.0111.0108

【 摘 要 】

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical buses across memory layers will likely be the first commercial application of 3D integrated circuit technology. The memory dies to stack together in a 3D memory are selected by a die-selection method. The conventional die-selection methods do not result in a high-enough yields of 3D memories because 3D memories are typically composed of known-good-dies (KGDs), which are repaired using self-contained redundancies. In 3D memory, redundancy sharing between neighboring vertical memory dies using TSVs is an effective strategy for yield enhancement. With the redundancy sharing strategy, a known-bad-die (KBD) possibly becomes a KGD after bonding. In this paper, we propose a novel die-selection method using KBDs as well as KGDs for yield enhancement in 3D memory. The proposed die-selection method uses three search-space conditions, which can reduce the search space for selecting memory dies to manufacture 3D memories. Simulation results show that the proposed die-selection method can significantly improve the yield of 3D memories in various fault distributions.

   

【 参考文献 】

• [1]V.F. Pavlidis and E.G. Friedman, "Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits," Proc. IEEE, vol. 97, no. 1, Jan. 2009, pp. 123-140.
• [2]H. Sun et al., "3D DRAM Design and Application to 3D Multicore Systems," IEEE Design Test Comput., vol. 26, no. 5, Sept. 2009, pp. 36-47.
• [3]W.R. Davis et al., "Demystifying 3D ICs: the Pros and Cons of Going Vertical," IEEE Design Test Comput., vol. 22, no. 6, Nov. 2005, pp. 498-510.
• [4]E.J. Marinissen and Y. Zorian, "Testing 3D Chips Containing Through-Silicon Vias," Proc. Int. Test Conf., Nov. 2009, pp. 1-11.
• [5]H.-H.S. Lee and K. Chakrabarty, "Test Challenges for 3D Integrated Circuits," IEEE Design Test Comput., vol. 26, no. 5, Sept. 2009, pp. 26-35.
• [6]S.S. Iyer et al., "Process-Design Considerations for Three Dimensional Memory Integration," Proc. Symp. VLSI Tech., June 2009, pp. 60-63.
• [7]Y.-F. Chou, D.-M. Kwai, and C.-W. Wu, "Memory Repair by Die Stacking with Through Silicon Vias," Proc. Int. Workshop Memory Tech., Design, and Testing, Aug. 2009, pp. 53-58.
• [8]L. Jiang, R. Ye, and Q. Xu, "Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing across Dies," Proc. Int. Conf. Comput.-Aided Design, Nov. 2010, pp. 230-234.
• [9]C.-W. Chou, Y.-J. Huang, and J.-F. Li, "Yield-Enhancement Techniques for 3D Random Access Memories," Proc. Int. Symp. VLSI Design Automat. Test, Apr. 2010, pp. 104-107.
• [10]T. Yamagata et al., "A Distributed Globally Replaceable Redundancy Scheme for Sub-Half-Micron ULSI Memories and Beyond," IEEE J. Solid-State Circuits, vol. 31, no. 2, Feb. 1996, pp. 195-201.
• [11]C.-T. Huang et al., "Built-In Redundancy Analysis for Memory Yield Improvement," IEEE Trans. Relia., vol. 52, no. 4, Dec. 2003, pp. 386-399.
• [12]M.-H. Yang et al., "A Novel BIRA Method with High Repair Efficiency and Small Hardware Overhead," ETRI J., vol. 31, no. 3, June 2009, pp. 339-341.
• [13]W. Jeong et al., "A Fast Built-In Redundancy Analysis for Memories with Optimal Repair Rate Using a Line-Based Search Tree," IEEE Trans. Very Large Scale Integr. Syst., vol. 17, no. 12, Dec. 2009, pp. 1665-1678.
• [14]H. Cho, W. Kang, and S. Kang, "A Built-In Redundancy Analysis with a Minimized Binary Search Tree," ETRI J., vol. 32, no. 4, Aug. 2010, pp. 638-641.
• [15]T. Han et al., "High Repair Efficiency BIRA Algorithm with a Line Fault Scheme," ETRI J., vol. 32, no. 4, Aug. 2010, pp. 642-644.
• [16]W. Jeong et al., "An Advanced BIRA for Memories with an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 12, Dec. 2010, pp. 2014-2026.