Yield Enhancement Techniques for 3D Memories by Redundancy Sharing among All Layers

ETRI Journal

关键词: die-selection method;    inter-die redundancy;    redundancy sharing;    multi-layer 3D memory;    Yield enhancement;   

Others  :  1186373
DOI  :  10.4218/etrij.12.0111.0643

【 摘 要 】

Three-dimensional (3D) memories using through-silicon vias (TSVs) will likely be the first commercial applications of 3D integrated circuit technology. A 3D memory yield can be enhanced by vertical redundancy sharing strategies. The methods used to select memory dies to form 3D memories have a great effect on the 3D memory yield. Since previous die-selection methods share redundancies only between neighboring memory dies, the opportunity to achieve significant yield enhancement is limited. In this paper, a novel die-selection method is proposed for multi-layer 3D memories that shares redundancies among all of the memory dies by using additional TSVs. The proposed method uses three selection conditions to form a good multi-layer 3D memory. Furthermore, the proposed method considers memory fault characteristics, newly detected faults after bonding, and multiple memory blocks in each memory die. Simulation results show that the proposed method can significantly improve the multi-layer 3D memory yield in a variety of situations. The TSV overhead for the proposed method is almost the same as that for the previous methods.

   

【 参考文献 】

• [1]V.F. Pavlidis and E.G. Friedman, “Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits,” Proc. IEEE, vol. 97, no. 1, Jan. 2009, pp. 123-140.
• [2]W.R. Davis et al., “Demystifying 3D ICs: The Pros and Cons of Going Vertical,” IEEE Design Test Comput., vol. 22, no. 6, Nov. 2005, pp. 498-510.
• [3]H. Sun et al., “3D DRAM Design and Application to 3D Multicore Systems,” IEEE Design Test Comput., vol. 26, no. 5, Sept. 2009, pp. 36-47.
• [4]S.S. Iyer et al., “Process-Design Considerations for Three Dimensional Memory Integration,” Proc. Symp. VLSI Tech., Jun. 2009, pp. 60-63.
• [5]E.J. Marinissen and Y. Zorian, “Testing 3D Chips Containing Through-Silicon Vias,” Proc. Int. Test Conf. (ITC), Nov. 2009, pp. 1-11.
• [6]H.-H.S. Lee and K. Chakrabarty, “Test Challenges for 3D Integrated Circuits,” IEEE Design Test Comput., vol. 26, no. 5, Sept. 2009, pp. 26-35.
• [7]Y.-F. Chou, D.-M. Kwai, and C.-W. Wu, “Memory Repair by Die Stacking with Through Silicon Vias,” Proc. Int. Workshop Memory Tech., Design, and Testing (MTDT), Aug. 2009, pp. 53-58.
• [8]C.-W. Chou, Y.-J. Huang, and J.-F. Li, “Yield-Enhancement Techniques for 3D Random Access Memories,” Proc. Int. Symp. VLSI Design Automat. Test (VLSI-DAT), Apr. 2010, pp. 104-107.
• [9]L. Jiang, R. Ye, and Q. Xu, “Yield Enhancement for 3D-Stacked Memory by Redundancy Sharing Across Dies,” Proc. Int. Conf. Comput.-Aided Design (ICCAD), Nov. 2010, pp. 230-234.
• [10]J. Lee, K. Park, and S. Kang, “A Die-Selection Method Using Search-Space Conditions for Yield Enhancement in 3D Memory,” ETRI J., vol. 33, no. 6, Dec. 2011, pp. 904-913.
• [11]T. Yamagata et al., “A Distributed Globally Replaceable Redundancy Scheme for Sub-Half-Micron ULSI Memories and Beyond,” IEEE J. Solid-State Circuits, vol. 31, no. 2, Feb. 1996, pp. 195-201.
• [12]C.-T. Huang et al., “Built-in Redundancy Analysis for Memory Yield Improvement,” IEEE Trans. Relia., vol. 52, no. 4, Dec. 2003, pp. 386-399.
• [13]M.-H. Yang et al., “A Novel BIRA Method with High Repair Efficiency and Small Hardware Overhead,” ETRI J., vol. 31, no. 3, June 2009, pp. 339-341.
• [14]W. Jeong et al., “A Fast Built-in Redundancy Analysis for Memories with Optimal Repair Rate Using a Line-Based Search Tree,” IEEE Trans. Very Large Scale Integr. Syst., vol. 17, no. 12, Dec. 2009, pp. 1665-1678.
• [15]H. Cho, W. Kang, and S. Kang, “A Built-In Redundancy Analysis with a Minimized Binary Search Tree,” ETRI J., vol. 32, no. 4, Aug. 2010, pp. 638-641.
• [16]T. Han et al., “High Repair Efficiency BIRA Algorithm with a Line Fault Scheme,” ETRI J., vol. 32, no. 4, Aug. 2010, pp. 642-644.
• [17]W. Jeong et al., “An Advanced BIRA for Memories with an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 12, Dec. 2010, pp. 2014-2026.
• [18]A. Papanikolaou, D. Soudris, and R. Radojcic, Three Dimensional System Integration: IC Stacking Process and Design, Springer, 2010.
• [19]C.H. Stapper, “On a Composite Model to the IC Yield Problem,” IEEE J. Solid-State Circuits, vol. 10, no. 6, Dec. 1975, pp. 537-539.
• [20]C.H. Stapper, A.N. McLaren, and M. Dreckmann, “Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product,” IBM J. Research Development, vol. 24, no. 3, May 1980, pp. 398-409.
• [21]C.-L. Wey and F. Lombardi, “On the Repair of Redundant RAM’s,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 6, no. 2, Mar. 1987, pp. 222-231.
• [22]R.-F. Huang et al., “A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories,” Proc. Int. Workshop Memory Tech., Design, and Testing (MTDT), Jul. 2002, pp. 68-73.