期刊论文详细信息
ETRI Journal
High Repair Efficiency BIRA Algorithm with a LineFault Scheme
关键词: repair efficiency;    memory yield;    Built-in redundancy analysis (BIRA);   
Others  :  1185931
DOI  :  10.4218/etrij.10.0210.0097
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【 摘 要 】

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes built-in redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

【 授权许可】

   

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【 参考文献 】
  • [1]S.Y. Kuo and W. Kent Fuchs, "Efficient Spare Allocation for Reconfigurable Arrays," IEEE Des. Test, vol. 4, no. 1, 1987, pp. 24-31.
  • [2]C.H. Huang et al., "Built-In Redundancy Analysis for Memory Yield Improvement," IEEE Trans. Reliab., vol. 52, no. 4, Dec. 2003, pp. 386-399.
  • [3]M. Yang et al., "A Novel BIRA Method with High Repair Efficiency and Small Hardware Overhead," ETRI J., vol. 31, no. 3, June 2009, pp. 339-341.
  • [4]T. Kawagoe et al., "A Built-In Self-Repair Analyzer (CRESTA) for Embedded DRAMs," Proc. Int. Test Conf., Oct. 2000, pp. 567-574.
  • [5]W. Jeong et al., "A Fast Built-in Redundancy Analysis for Memories with Optimal Repair Rate Using a Line-Based Search Tree," IEEE Trans. Very Large Scale Integration, vol. 17, no. 12, Dec. 2009, pp. 1665-1678.
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