A 1.2 V 12 b 60 MS/s CMOS Analog Front-End for Image Signal Processing Applications

ETRI Journal

关键词: low power;    low voltage;    flexibility;    power management technique;    programmable capacitor array scheme;    op-amp preset technique;    ADC;    VGA;    AFE;   

Others  :  1185745
DOI  :  10.4218/etrij.09.1209.0025

【 摘 要 】

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 um CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 mm² and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

   

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