期刊论文详细信息
ETRI Journal
A Low-Complexity 128-Point Mixed-Radix FFT Processor for MB-OFDM UWB Systems
关键词: ultra-wideband (UWB);    substructure-sharing multiplication unit (SMU);    complex constant multiplier (CCM);    mixed-radix;    Fast Fourier transform (FFT);   
Others  :  1185981
DOI  :  10.4218/etrij.10.0109.0232
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【 摘 要 】

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-24 algorithm and a radix-23 algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 µm CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

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【 参考文献 】
  • [1]A. Batra et al., "Design of a Multiband OFDM System for Realistic UWB Channel Environments," IEEE Trans. Microw. Theory Tech., vol. 52, no. 9, Sept. 2004, pp. 2123-2138.
  • [2]K.M. Kang and S.S. Choi, "Initial Timing Acquisition for Binary Phase-Shift Keying Direct Sequence Ultra-wideband Transmission," ETRI Journal, vol. 30, no. 4, Aug. 2008, pp. 495-505.
  • [3]W. Abbott et al., Multiband OFDM Physical Layer Specification, Version 1.2 (draft), WiMedia Alliance, Feb. 2007.
  • [4]Y.W. Lin, H.Y. Liu, and C.Y. Lee, "A 1-GS/s FFT/IFFT Processor for UWB Applications," IEEE J. Solid-State Circuits, vol. 40, no. 8, Aug. 2005, pp. 1726-1735.
  • [5]S.I. Cho, K.M. Kang, and S.S. Choi, "Implementation of 128-Point Fast Fourier Transform Processor for UWB Systems," Proc. IEEE IWCMC, Aug. 2008, pp. 210-213.
  • [6]J.S. Lee et al. "A High-Speed, Low-Complexity Radix-24 FFT Processor for MB-OFDM UWB Systems," Proc. IEEE ISCAS, May 2006, pp. 4719-4722.
  • [7]T.S. Chakraborty and S. Chakrabarti, "A Reduced Area 1 GSPS FFT Design Using MRMDF Architecture for UWB Communication," Proc. IEEE APCCAS, Nov. 2008, pp. 1128-1131.
  • [8]Z. Wang et al., "A Novel FFT Processor for OFDM UWB Systems," Proc. IEEE APCCAS, Dec. 2006, pp. 374-377.
  • [9]S. Qiao et al., "An Area and Power Efficient FFT Processor for UWB Systems," Proc. IEEE WICOM, Sept. 2007, pp. 582-585.
  • [10]J. García, J.A. Michel, and A.M. Burón, "VLSI Configurable Delay Commutator for a Pipeline Split Radix FFT Architecture," IEEE Trans. Signal Process., vol. 47, no. 11, Nov. 1999, pp. 3098-3107.
  • [11]K. Maharatna, E. Grass, and U. Jagdhold, "A 64-Point Fourier Transform Chip for High-Speed Wireless LAN Application Using OFDM," IEEE J. Solid-State Circuits, vol. 39, no. 3, Mar. 2004, pp. 484-493.
  • [12]C.-P. Fan, M.-S. Lee, and G.-A. Su, "A Low Multiplier and Multiplication Costs 256-Point FFT Implementation with Simplified Radix-24 SDF Architecture," Proc. IEEE APCCAS, Dec. 2006, pp. 1935-1938.
  • [13]K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, New York; John Wiley & Sons, 1999.
  • [14]G. Zhong et al., "An Energy-Efficient Reconfigurable Angle-Rotator Architecture," Proc. IEEE ISCAS, vol. 3, May 2004, pp. 661-664.
  • [15]C.H. Shin et al., "A Design and Performance of 4-Parallel MB-OFDM UWB Receiver," IEICE Trans. Commun., vol. E90-B, no. 3, Mar. 2007, pp. 672-675.
  • [16]S.W. Choi, K.M. Kang, and S.S. Choi, "A Two-Stage Radix-4 Viterbi Decoder for Multiband OFDM UWB Systems," ETRI Journal, vol. 30, no. 6, Dec. 2008, pp. 850-852.
  • [17]K.J. Cho et al., "Design of Low-Error Fixed-Width Modified Booth Multiplier," IEEE Trans. VLSI Syst., vol. 12, no. 5, May 2004, pp. 522-531.
  • [18]S.M. Kim, J.G. Chung, and K.K. Parhi, "Low Error Fixed-Width CSD Multiplier with Efficient Sign Extension," IEEE Trans. Circuits & Systems II, vol. 50, no. 12, Dec. 2003, pp. 984-993.
  • [19]Y. Jung, H. Yoon, and J. Kim, "New Efficient FFT Algorithm and Pipeline Implementation Results for OFDM/DMT Applications," IEEE Trans. Consumer Elect., vol. 49, no. 1, Feb. 2003, pp. 14-20.
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